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An amplitude detector for variable frequency sinusoidal signals
Author(s)
Date Issued
December 1, 2006
Type
Conference Paper
Abstract
In this paper, a JK-flip-flop-based logic circuit is described. Using two output signals of this designed logic circuit to control a buffered peak detector followed by a simple sample-and-hold circuit in sequential operation, a sinusoidal amplitude detector is proposed. The proposed detector allows the frequency of input signals to be varied over a wide range. Experimental results verifying the performances of the proposed circuit are in close agreement with the expected values. © 2006 ICASE.
Citation
2006 SICE Icase International Joint Conference, 4152-4155, 2006