Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling

Tongsima, Sissades; Chantrapornchai, Chantana; Sha, Edwin H.M.; Passos, Nelson L.

Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling

Author(s)

Tongsima, Sissades

Chantrapornchai, Chantana

Sha, Edwin H.M.

Passos, Nelson L.

Date Issued

December 1, 1998

Type

Article

Abstract

Computation intensive DSP applications usually require parallel/pipelined processors in order to meet specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for such DSP applications. This algorithm has been embedded in a tool, called SHARP, which schedules a pipelined data flow graph to multiple pipelined units while hiding the underlying data hazards and minimizing the execution time. This paper reports significant improvement for some well-known benchmarks showing the efficiency of the scheduling algorithm and the flexibility of the simulation tool.

Citation

Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 18(2), 111-123, 1998