An FPGA-based implementation of variable fractional delay filter

Nithirochananont, Ussanai; Chivapreecha, Sorawat; Dejhan, Kobchai

doi:10.1109/CSPA.2009.5069197

An FPGA-based implementation of variable fractional delay filter

Author(s)

Nithirochananont, Ussanai

Chivapreecha, Sorawat

Dejhan, Kobchai

Date Issued

October 19, 2009

Type

Conference Paper

DOI

10.1109/CSPA.2009.5069197

Abstract

A variable fractional delay (VFD) filter is widely used in applications such as symbol timing recovery, arbitrary sampling rate conversion and echo cancellation. This paper presents an implementation of variable fractional delay filter on FPGA. The implementation utilizes an efficient structure so called Taylor structure. The main advantage of this structure is to reduce number of multiplier and adder when compared with Farrow structure or modified Farrow structure. The result of implementation will be reported as throughput and area utilization. ©2009 IEEE.

Citation

Proceedings of 2009 5th International Colloquium on Signal Processing and Its Applications Cspa 2009, 104-107, 2009