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CMOS voltage-mode analog multiplier
Author(s)
Boonchu, Boonchai
Surakampontorn, Wanlop
Date Issued
December 1, 2006
Type
Conference Paper
Abstract
This paper proposes a CMOS voltage-mode four-quadrant analog multiplier. It is based on a pair of diode-connected MOS transistor that is biased with a constant current source, and a CMOS voltage difference circuit. Simulation results shows that the linear range is ±400 mV with the linearity error of 0.8% and the harmonic distortion of 0.62%. The -3dB bandwidth of 30MHz is achieved at the power consumption of 1.26mW. © 2006 IEEE.
Citation
Proceedings IEEE International Symposium on Circuits and Systems, 1989-1992, 2006