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Distributed clock gating for power reduction of a programmable waveform generator for neural stimulation
Author(s)
Date Issued
December 14, 2012
Type
Conference Paper
Abstract
This paper describes how to employ distributed clock gating to achieve an overall low power design of a programmable waveform generator intended for a neural stimulator. The power efficiency is enabled using global timing control combined with local amplitude distribution over a bus to the local stimulator frontends. This allows the combination of local and global clock gating for complete sub-blocks of the design. A counter and a shifter employed at the local digital stimulator reduce the design complexity for the waveform generation and thus the overall power consumptions. The average power results indicate that 63% power can be saved for the global stimulator control unit and 89-96% power can be saved for the local digital stimulator by using the proposed approach. The circuit has been implemented and successfully tested in a 0.35 μm AMS HVCMOS technology. © 2012 IEEE.
Citation
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society EMBS, 3878-3881, 2012