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A Logarithmic Level-Crossing ADC with Fixed Comparison Window
Author(s)
Thanachayanont, Apinunt
Date Issued
January 1, 2022
Type
Conference Paper
Abstract
This paper describes the design and realization of a logarithmic level-crossing analog-to-digital converter with fixed comparison window. The proposed circuit comprises two comparators, a logarithmic charge-sharing digital-to-analog converter, a control logic circuit, and an up/down counter. The circuit is designed and simulated with process parameters from a 0.18 μm CMOS technology and a 1.8 V power supply voltage. Simulation results showed that the overall circuit exhibited the minimum resolution of 3.9mV and the maximum INL and DNL errors of -0.17LSB and -0.09LSB, respectively.
Citation
19th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2022, 2022