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A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications
Author(s)
Sundarasaradula, Yuwadee
Constandinou, Timothy G.
Thanachayanont, Apinunt
Date Issued
January 1, 2016
Type
Conference Paper
Abstract
This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range.
Citation
2016 IEEE International Conference on Electronics Circuits and Systems Icecs 2016, 25-28, 2016