Test chip design and parameter extraction of parasitic capacitance of MOSFET in VLSI

Abstract

This article describes test ship design and parameter extraction of parasitic capacitance of MOSFET in VLSI. The test structure for separating area and side-wall capacitance components of N+Psub junction and P+Nwell junction are used as testing devices. The BSIM3v3 models are proposed also. The results suggest that the correlation was found in 2% level. The manual calculation should be used for the benefit of extraction methodology. Finally, the overall data should be a data base of the design tool kit which hand out to the circuit designer in Multi Project Chip.