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Metastability analysis of CMOS latch
Author(s)
Tooprakai, Paiboon
Dejhan, Kobchai
Mitatha, Somsak
Cheevasuvit, Fusak
Soonyeekan, Chatcharin
Date Issued
December 1, 1999
Type
Conference Paper
Abstract
This paper proposes an optimization and its effect of CMOS latch to carry out the optimum ratio of W/L without metastability problem. This proposed method is based on 0.8 mm CMOS technology, the speed and power dissipation are determined with small effect of layout areas.
Citation
International Symposium on IC Technology Systems and Applications, 8, 229-232, 1999