Voltage-mode threshold-independent analogue multiplier

Abstract

In this article, a new threshold-independent four-quadrant analogue multiplier is designed and developed. It is based on the square-law of the MOS transistor in the saturation region and quarter-square algebraic identity. The circuit structure uses voltage summing and voltage-mode squaring stages. By applying the reference voltage to the voltage summing stage, the threshold-independent multiplication function can be achieved. On the basis of the voltage-mode circuit structure, the proposed multiplier produces an output signal in voltage form without resistors. The performances of the proposed circuit have been simulated with PSPICE. Simulation results show that the multiplier has a wide band capability, where a-3dB bandwidth of 160MHz is achieved. The circuit has 0.75% linearity error and 0.47% total harmonic distortion under the maximum input voltage of 500mV at both multiplier inputs. The power consumption is about 0.5mW with a1.5V power supply voltage. To verify the performances of the proposed multiplier, experimental results with discrete transistor arrays are obtained. The results will be useful in analogue signal processing applications.