Extraction Methodology and Junction Capacitance Model of PMOSFET in VLSI

Abstract

The paper presents the extraction methodology and junction capacitance model of PMOSFET in VLSI. The p-n junction layouts with low perimeter and high perimeter have been designed. The LOCal Oxidation of Silicon (LOCOS) affect was used for the device area and perimeter be precisely determined. The C-V characteristics of P+/NWell junction, PLDD/NWell junction and Psub/NWell junction are measured. The model can be calculated by simple program which gives the error between the results of the measurement and the results of the simulation is in the range of less than 5%