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Design procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient
Author(s)
Thanachayanont, Apinunt
Date Issued
May 1, 2022
Type
Article
Abstract
This paper describes a design procedure that optimises for noise and power dissipation of CMOS folded-cascode operational transconductance amplifier. The proposed design procedure is derived based on the unified EKV MOSFET equation and employs the inversion coefficient and transconductance efficiency of MOSFET as the essential design parameters. Key specifications of operational amplifier and CMOS process parameters are used with the proposed procedure to calculate the circuit parameters. A MATLAB routine is written to execute the design steps and MATLAB simulations are carried out to show how the circuit parameters are affected by the noise requirements. Finally, transistor-level circuit simulations are performed with 0.13 μm CMOS process parameters to validate the efficacy of the proposed design procedure.
Citation
Analog Integrated Circuits and Signal Processing, 111(2), 201-214, 2022