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Application techniques for high performance ADC
Author(s)
Chuenarom, S.
Tipsuwampron, V.
Date Issued
December 1, 2006
Type
Conference Paper
Abstract
A current-mode technique for the design of algorithmic ADC is presented. The necessary voltage swing is given dynamic range to be reduced at the same time. It uses CMOS op-amp common with a current injection technique. The advantage of op-amp reduces current mismatches due to the device finite output resistance and injection current to increase the speed of current mirrors. In this paper that the advantages and disadvantages of different ADC algorithmic is designed of new algorithmic ADC for the output current of comparator. The objective is the development an increase performance ADC. The 6-bit ADC is implemented in 0.25μm CMOS technology. It has a conversion rate of 7.3MHz, a low power 2.5V, a power dissipation of 0.83mW with the differential nonlinearity (DNL,) of 0.29LSB and integral nonlinearity (INL) of 0.16LSB. © 2006 IEEE.
Citation
2006 International Symposium on Communications and Information Technologies Iscit, 749-752, 2006