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A current signal CMOS sample-and-hold circuit
Author(s)
Date Issued
December 1, 2007
Type
Conference Paper
Abstract
This article presents a current signal sample-and-hold (S/H) circuit using 0.5μm CMOS technology. A current minimum circuit is used to sample the input signal in place of a sampling switch used in the conventional S/H circuit. The current peak detector is used to hold the signal from the minimum circuit in the "hold" state. The proposed configuration is adopted effectively to cancel switch feedthrough error. The performances of the proposed circuit are demonstrated using the PSPICE analog simulation program. Simulation results show the sampling frequency up to 100MHz and high accuracy. © ICROS.
Citation
Iccas 2007 International Conference on Control Automation and Systems, 171-174, 2007