FPGA-based IC design for 3-phase PWM inverter with optimized space vector modulation schemes

Sangchai, Worranart; Wiangtong, Theerayod; Lumyong, Pichit

doi:10.1109/MWSCAS.2000.951597

FPGA-based IC design for 3-phase PWM inverter with optimized space vector modulation schemes

Author(s)

Sangchai, Worranart

Wiangtong, Theerayod

Lumyong, Pichit

Date Issued

January 1, 2000

Type

Article

DOI

10.1109/MWSCAS.2000.951597

Abstract

This paper presents a novel idea to integrate three of the Space Vector Modulation (SVM) schemes, including the alternating zero sequence, the symmetric sequence and the bus clamped, in only a single FPGA chip which provides many advantages. Flexibility, reliability and very compact system are obviously obtained from this designed chip. Moreover, faster design and verification time, design change without penalty are also the benefits resulted in FPGA-Based IC design. The optimized SVM schemes, frequencies and programmable deadtime that used to adjust output signals are obtained through either 4×4 keypad or microprocessor port.

Citation

Midwest Symposium on Circuits and Systems, 1, 106-109, 2000