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A comparative investigation of a pentacene layer on gold and PMMA in bottom-contact pentacene thin film transistors
Author(s)
Tippo, Tossapol
Thanachayanont, Chanchana
Nakajima, Hideki
Songsiriritthigul, Prayoon
Hietschold, Micheal
Thanachayanont, Apinunt
Date Issued
October 29, 2013
Type
Conference Paper
Abstract
This study demonstrates an attempt to fabricate the 25 μ channel-length bottom-contact pentacene TFTs using thermal evaporation through shadow mask technique and to investigate crystal structure, morphology and electronic structure of the pentacene layer deposited at the same time on gold (Au) source-drain electrodes and Poly(methyl methacrylate) (PMMA) gate-dielectric of the TFTs. The pentacene layers with thicknesses of 50 nm were deposited at the evaporation rates of 0.1, 0.5, 1.0 and 1.5 nm/min at substrate temperatures of 60 °C. These conditions were employed with and without preheating at 80 °C before deposition. Preheating at 80 °C was found to improve quality of the pentacene film on the PMMA gate-dielectric. Using the deposition rate of 1 nm/min and the substrate temperature of 60 °C, best performance of TFTs were obtained. At this deposition condition, pentacene film work function was found to be higher on the Au source-drain electrodes than on the PMMA gate-dielectric. © (2013) Trans Tech Publications, Switzerland.
Citation
Advanced Materials Research, 802, 27-31, 2013
Subjects