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A 0.7-V, 2.86-μW low-noise logarithmic amplifier for neural recording system
Author(s)
Sundarasaradula, Yuwadee
Thanachayanont, Apinunt
Date Issued
December 1, 2013
Type
Conference Paper
Abstract
This paper describes the design and realization of a low-noise, low-voltage, low-power CMOS logarithmic amplifier for bio-signal and neural recording applications. The proposed logarithmic amplifier is based on the progressive-compression parallel-summation architecture with DC offset cancellation feedback loop. A new fully differential limiting amplifier with bulk-driven current mirror active load is proposed to achieve larger voltage gain and low voltage operation. The proposed logarithmic amplifier was designed and simulated with process parameters from a standard 0.18-μm CMOS technology. The circuit operates with a single 0.7-V power supply voltage and dissipates 2.86 μW. The simulated input dynamic range is about 60 dB, which covers the input amplitudes ranging from 10 μV to 10 mV. The simulated -3-dB bandwidth of the amplifier is from 0.32 Hz to 22 kHz. The simulated total input-referred noise, integrated from 0.1 Hz to 10 kHz, is 4.41 μV. © 2013 IEEE.
Citation
IEEE Region 10 Annual International Conference Proceedings TENCON, 2013