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A 1-V, 330-nW, 6-Bit Current-Mode Logarithmic Cyclic ADC for ISFET-Based pH Digital Readout System
Author(s)
Thanachayanont, Apinunt
Date Issued
May 1, 2015
Type
Article
Abstract
This paper describes the design and implementation of a low-power current-mode logarithmic analog-to-digital converter (ADC) for an ISFET-based $$p\!H$$pH digital readout system. The system comprises a front-end ISFET-based $$p\!H$$pH readout circuit and a succeeding logarithmic ADC to produce a digital output signal which is linearly related to the input $$p\!H$$pH variation. The front-end $$p\!H$$pH readout circuit is realized using a subthreshold ISFET/REFET differential pair with a current-mode translinear multiplier/divider circuit. The logarithmic ADC is realized using the cyclic architecture and current-mode circuit techniques to achieve low power dissipation. High-accuracy current sample-and-hold circuit based on the regulated-cascode switched-current memory cell and low-power high-resolution current comparator are proposed for the ADC realization. All circuits were designed to operate with a single 1-V power supply voltage, and were simulated with process parameters from a 0.18-$$\mu $$μm CMOS technology. The power dissipation of the front-end $$p\!H$$pH readout circuit and the logarithmic ADC is 20 and 330 nW, respectively. The front-end $$p\!H$$pH readout circuit can produce an output current range of 0.1–300 nA which is logarithmically corresponded to the input $$p\!H$$pH range of 4–10. The logarithmic ADC operates with 1-kS/s sampling rate and achieves the integral nonlinearity error of $$\pm 0.8$$±0.8 LSB, the effective number of bits of 5.95, and 37.6-dB of signal-to-noise-distortion ratio with 100-nA full-scale input range.
Citation
Circuits Systems and Signal Processing, 34(5), 1405-1429, 2015