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Optimization of multithread for long digit multiplier: By using ancient India Vedic mathematic
Author(s)
Thongbai, Nopphagaw
Date Issued
November 3, 2017
Type
Conference Paper
Abstract
Any processor's performance is dependent on three important factor speed, area and power. The better tread-off between factors, an effective once. Multiplier are common used in computation process. In this paper, the proposed multiplier by design based on the sutra 'Urdhva Tiryakbhyam and Nikhilam' of Vedic are analyzed and the performance results of multiplier are compare with conventional multipliers and karatsuba once of the most popular. In conclusion of experiment Vedic mathematics can be improvement computation effective. Specifically, in accurate computation, in many digit mathematics or very long digit, that want power of computation. By helping of special opcode instruction that bundle in processor such as SSE, AVX and etc. in modern processor to increment parallel process level in single core by SIMD and vector register.
Citation
Ecti Con 2017 2017 14th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology, 652-655, 2017