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A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications
Author(s)
Sundarasaradula, Yuwadee
Thanachayanont, Apinunt
Date Issued
June 30, 2018
Type
Article
Abstract
This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18μm CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027mm2. The overall circuit consumes 9.75μW from a single 1.5V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80dB input dynamic range (from 10μV to 100mV), a bandwidth of 4Hz-10kHz, and a total input-referred noise of 5.52μV.
Citation
Journal of Circuits Systems and Computers, 27(7), 2018