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A design of four-quadrant analog multiplier
Author(s)
Date Issued
December 1, 2004
Type
Conference Paper
Abstract
This paper proposes a new four quadrants analog multiplier which consists of a multiplier cell, a mixed signal circuit and three signal subtraction circuits. Its advantages are : this design has single ended inputs, the geometry of all transistors are equal, and its output can be the product of two signal voltage, or the product of a signal current and a signal voltage. Simulation results are demonstrated by PSpice to confirm the operation of the circuit.
Citation
IEEE International Symposium on Communications and Information Technologies Iscit 2004, 1, 29-32, 2004