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Capacity Enhancement of Asymmetric Multi-Level Cell (MLC) NAND Flash Memory using Write Voltage Optimization
Author(s)
Date Issued
June 1, 2019
Type
Conference Paper
Abstract
In NAND flash memory, the number of bits per cell is increased to enhance the storage density, however, the reliability of NAND flash memory will be degraded. The current research only focuses on the read voltage optimization and advanced error-correction codes. The investigation of the write voltages optimization is limited. Since the write voltages significantly affect the channel capacity, we propose the write voltage optimization to enhance the channel capacity of MLC NAND flash memory. The differential evolution algorithm is applied to find the optimal write voltage that provide the maximum channel capacity.
Citation
34th International Technical Conference on Circuits Systems Computers and Communications Itc Cscc 2019, 2019