A versatile dual-mode transposition latch array design for DCT in HDTV applications

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dc.contributor.authorDejhan, K.
dc.contributor.authorCheevasuvit, F.
dc.contributor.authorTrisuwannawat, T.
dc.contributor.authorKaneko, M.
dc.date.accessioned2026-08-06T09:49:52Z
dc.date.available2026-08-06T09:49:52Z
dc.date.issued1992-01-01
dc.description.abstractA versatile optimal dual-mode matrix transposer using latch for the design of data format converter has been developed with optimization of latch/static register. The architecture has been designed with 1.2μm HCM0S3 technology for the best speed/area/power tradeoff. © 1992 IEEE
dc.identifier.citationIEEE Transactions on Consumer Electronics, 38(4), 812-818, 1992
dc.identifier.doi10.1109/30.179970
dc.identifier.issn00983063
dc.identifier.other2-s2.0-84942486535
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/97
dc.sourceIEEE Transactions on Consumer Electronics
dc.titleA versatile dual-mode transposition latch array design for DCT in HDTV applications
dc.typeArticle

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