A ± 1.5 V high frequency four quadrant current multiplier
| dc.contributor.author | Arthansiri, Teerawat | |
| dc.contributor.author | Kasemsuwan, Varakorn | |
| dc.contributor.author | Ahn, Hyung Keun | |
| dc.date.accessioned | 2026-08-06T09:53:46Z | |
| dc.date.available | 2026-08-06T09:53:46Z | |
| dc.date.issued | 2005-12-01 | |
| dc.description.abstract | This paper presents a four quadrant current multiplier based on the square-law characteristic of MOS transistor operating in the saturation region. The current multiplier consists of four quadratic cells using only NMOS transistor. The circuit operates using the supply voltages of ± 1.5 V and with the quiescent current of 25 μA. The nonlinearity is 0.36 % when the input current is the same as the bias current and reduced to only 0.1 % when input current is reduced by half. The cut-off frequency is 413 MHz with a total harmonic distortion less than 0.15 % (at 1 MHz). The power dissipation is 0.45 mW. © 2005 IEEE. | |
| dc.identifier.citation | Proceedings IEEE International Symposium on Circuits and Systems, 1016-1019, 2005 | |
| dc.identifier.doi | 10.1109/ISCAS.2005.1464763 | |
| dc.identifier.issn | 02714310 | |
| dc.identifier.other | 2-s2.0-33645565706 | |
| dc.identifier.uri | https://dspace.kmitl.ac.th/handle/123456789/1191 | |
| dc.source | Proceedings IEEE International Symposium on Circuits and Systems | |
| dc.title | A ± 1.5 V high frequency four quadrant current multiplier | |
| dc.type | Conference Paper |