A 4-bit ultra-wideband complementary metal-oxide-semiconductor attenuator with low root-mean-square amplitude error

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dc.contributor.authorPakasiri, Chatrpol
dc.contributor.authorZhu, Fu Sheng
dc.contributor.authorWang, Sen
dc.date.accessioned2026-08-06T10:26:19Z
dc.date.available2026-08-06T10:26:19Z
dc.date.issued2019-11-01
dc.description.abstractThis article presents the 4-bit ultra-wideband complementary metal-oxide-semiconductor (CMOS) attenuator in a standard 0.18-μm CMOS process. This design adopts switched bridge-T type topologies for each attenuation bit. Based on insertion losses and input P<inf>1-dB</inf> considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5-4-2-1 dB is employed in the 4-bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root-mean-square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P<inf>1-dB</inf> is 15 dBm at 5 GHz and the chip area is 1.12 mm<sup>2</sup> including all testing pads.
dc.identifier.citationInternational Journal of RF and Microwave Computer Aided Engineering, 29(11), 2019
dc.identifier.doi10.1002/mmce.21922
dc.identifier.issn10964290
dc.identifier.other2-s2.0-85070663693
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/10344
dc.sourceInternational Journal of RF and Microwave Computer Aided Engineering
dc.subjectattenuator
dc.subjectCMOS
dc.subjectRMS amplitude error
dc.subjectultra-wideband
dc.titleA 4-bit ultra-wideband complementary metal-oxide-semiconductor attenuator with low root-mean-square amplitude error
dc.typeArticle

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