CMOS class-AB voltage-mode multiplier

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dc.contributor.authorBoonchu, Boonchai
dc.contributor.authorSurakampontorn, Wanlop
dc.date.accessioned2026-08-06T09:53:43Z
dc.date.available2026-08-06T09:53:43Z
dc.date.issued2005-12-01
dc.description.abstractA novel circuit configuration for a CMOS voltage-mode four-quadrant analog multiplier is described. It is based on square law characteristic of MOS transistor and class-AB amplifier. The multiplier achieves a linearity of 1.1%, -3dB bandwidth of 35MHz, and a total harmonic distortion of 0.76%. The power consumption is 1.5mW. © 2005 IEEE.
dc.identifier.citationIscit 2005 International Symposium on Communications and Information Technologies 2005 Proceedings, I, 1489-1492, 2005
dc.identifier.doi10.1109/ISCIT.2005.1567165
dc.identifier.other2-s2.0-33750100175
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/1177
dc.sourceIscit 2005 International Symposium on Communications and Information Technologies 2005 Proceedings
dc.subjectClass-AB
dc.subjectMultiplier
dc.titleCMOS class-AB voltage-mode multiplier
dc.typeConference Paper

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