Comparative study on cascade control configuration in engineering phase for analog system and FF system

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dc.contributor.authorNarupon Khochasin
dc.contributor.authorThanit Trisuwannawat
dc.contributor.authorPrasit Julsereewong
dc.contributor.authorAmphawan Julsereewong
dc.date.accessioned2025-07-21T05:57:28Z
dc.date.issued2016-12-01
dc.identifier.doi10.1109/sii.2016.7844111
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/6059
dc.subjectInterlock
dc.subject.classificationIntegrated Circuits and Semiconductor Failure Analysis
dc.titleComparative study on cascade control configuration in engineering phase for analog system and FF system
dc.typeArticle

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