FPGA-based cuckoo hashing for pattern matching in NIDS/NIPS

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dc.contributor.authorTran, Thinh Ngoc
dc.contributor.authorKittitornkun, Surin
dc.date.accessioned2026-08-06T09:55:05Z
dc.date.available2026-08-06T09:55:05Z
dc.date.issued2007-01-01
dc.description.abstractPattern matching for network intrusion/prevention detection demands exceptionally high throughput with recent updates to support new attack patterns. This paper describes a novel FPGA-based pattern matching architecture using a recent hashing algorithm called Cuckoo Hashing. The proposed architecture features on-the-fly pattern updates without reconfiguration, more efficient hardware utilization, and higher throughput. Through various algorithmic changes of Cuckoo Hashing, we can implement parallel pattern matching on SRAM-based FPGA. Our system can accommodate the newest Snort rule-set, an open source Network Intrusion Detection/Prevention System, and achieve the highest utilization in terms of SRAM per character and Logic Cells per character at 15.63 bits/character and 0.033 Logic Cells/character, respectively on major Xilinx Virtex FPGA architectures. Compared to others, ours is more efficient than any other Xilinx FPGA architectures. © Springer-Verlag Berlin Heidelberg 2007.
dc.identifier.citationLecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 4773 LNCS, 334-343, 2007
dc.identifier.doi10.1007/978-3-540-75476-3_34
dc.identifier.issn03029743
dc.identifier.other2-s2.0-38149004833
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/1569
dc.sourceLecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics
dc.subjectCuckoo hashing
dc.subjectFPGA
dc.subjectNIDS
dc.subjectNIPS
dc.subjectPattern matching
dc.titleFPGA-based cuckoo hashing for pattern matching in NIDS/NIPS
dc.typeConference Paper

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