A CMOS log-antilog current multiplier/divider circuit using DDCC

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dc.contributor.authorTorteanchai, Usa
dc.contributor.authorKumngern, Montree
dc.contributor.authorDejhan, Kobchai
dc.date.accessioned2026-08-06T10:03:25Z
dc.date.available2026-08-06T10:03:25Z
dc.date.issued2011-12-01
dc.description.abstractThis paper presents a new one-quadrant analog log-antilog multiplier/divider using only one differential different current conveyor and four diodes. The proposed circuit features low circuit complexity, very suitable for integrated circuit implementation and excellent temperature stability. Simulation results show performance of the circuit and confirm the validity of the proposed design technique. © 2011 IEEE.
dc.identifier.citationIEEE Region 10 Annual International Conference Proceedings TENCON, 634-637, 2011
dc.identifier.doi10.1109/TENCON.2011.6129184
dc.identifier.other2-s2.0-84856865342
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/3948
dc.sourceIEEE Region 10 Annual International Conference Proceedings TENCON
dc.subjectCMOS
dc.subjectdifferential difference current conveyor
dc.subjectlog-antilog multiplier
dc.titleA CMOS log-antilog current multiplier/divider circuit using DDCC
dc.typeConference Paper

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