Multiplier-less and compact FPGA implementation of Mihalas-Niebur neuron

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dc.contributor.authorKongpoon, Metha
dc.contributor.authorLeelavattananon, Kritsapon
dc.date.accessioned2026-08-06T10:26:15Z
dc.date.available2026-08-06T10:26:15Z
dc.date.issued2019-11-01
dc.description.abstractThe modified Mihalas-Niebur neuron model suitable for a compact digital implementation is presented. Based on the modified model, a multiplier-less and compact Mihalas-Niebur neuron that uses word-length optimization and bitwise shifting operators for the multiplication was designed and implemented on an FPGA. The simulation results show that the proposed neuron successfully produces all 20 prominent spiking patterns with a few FPGA resources used.
dc.identifier.citationProceedings Apccas 2019 2019 IEEE Asia Pacific Conference on Circuits and Systems Innovative CAS Towards Sustainable Energy and Technology Disruption, 321-324, 2019
dc.identifier.doi10.1109/APCCAS47518.2019.8953116
dc.identifier.other2-s2.0-85078705729
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/10328
dc.sourceProceedings Apccas 2019 2019 IEEE Asia Pacific Conference on Circuits and Systems Innovative CAS Towards Sustainable Energy and Technology Disruption
dc.subjectcompact implementation
dc.subjectFPGA
dc.subjectMihalas-Niebur neuron
dc.subjectmultiplier-less neuron
dc.titleMultiplier-less and compact FPGA implementation of Mihalas-Niebur neuron
dc.typeConference Paper

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