Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing

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dc.contributor.authorSato, Tomoaki
dc.contributor.authorChivapreecha, Sorawat
dc.contributor.authorHiguchi, Kohji
dc.contributor.authorMoungnoul, Phichet
dc.date.accessioned2026-08-06T10:22:34Z
dc.date.available2026-08-06T10:22:34Z
dc.date.issued2018-12-24
dc.description.abstractMachine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAS, wave-pipeline techniques can be introduced for further high through put processing. In order to further improve the performance of wave-pipelines on the FPGAS, fine-Tuning should be executed. A fine-Tuning tool essential for realizing these is developed.
dc.identifier.citationIscit 2018 18th International Symposium on Communication and Information Technology, 204-207, 2018
dc.identifier.doi10.1109/ISCIT.2018.8587986
dc.identifier.other2-s2.0-85060971227
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/9320
dc.sourceIscit 2018 18th International Symposium on Communication and Information Technology
dc.subjectASIC-FPGA architecture
dc.subjectfine-Tuning
dc.subjectFPGA
dc.subjectGPU
dc.subjectmachine learning
dc.subjectRTL design
dc.subjectwave-pipeline
dc.titleDesigning a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing
dc.typeConference Paper

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