A linearized source-couple pair transconductor using a low-voltage square root circuit

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dc.contributor.authorNgamkham, W.
dc.contributor.authorKiatwarin, N.
dc.contributor.authorNarksap, W.
dc.contributor.authorSangpisit, W.
dc.contributor.authorKiranon, W.
dc.date.accessioned2026-08-06T09:56:59Z
dc.date.available2026-08-06T09:56:59Z
dc.date.issued2008-10-06
dc.description.abstractThis paper presents a CMOS transconductor linearization by connecting square-rooter to a source couple pair circuit. A novel square-rooting circuit is proposed for low voltage operation. The proposed transconductance circuit is compact and consumes lower quiescent power, compared with the existing transconductors using the same realization technique. The circuit performances verification by PSPICE simulations show good results as expected. © 2008 IEEE.
dc.identifier.citation5th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2008, 2, 701-704, 2008
dc.identifier.doi10.1109/ECTICON.2008.4600527
dc.identifier.other2-s2.0-52949134836
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/2107
dc.source5th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2008
dc.titleA linearized source-couple pair transconductor using a low-voltage square root circuit
dc.typeConference Paper

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