Multiplier-less and compact FPGA implementation of Mihalas-Niebur neuron

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dc.contributor.authorMetha Kongpoon
dc.contributor.authorKritsapon Leelavattananon
dc.date.accessioned2025-07-21T06:02:29Z
dc.date.issued2019-11-01
dc.identifier.doi10.1109/apccas47518.2019.8953116
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/8863
dc.subjectBiological neuron model
dc.subjectBitwise operation
dc.subject.classificationAdvanced Memory and Neural Computing
dc.titleMultiplier-less and compact FPGA implementation of Mihalas-Niebur neuron
dc.typeArticle

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