An on-chip delay measurement using adjacency testable scan design

Simple item page
dc.contributor.authorKentaro Kato
dc.contributor.authorSomsak Choomchuay
dc.date.accessioned2025-07-21T05:56:14Z
dc.date.issued2015-10-01
dc.identifier.doi10.1109/iciteed.2015.7409000
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/5355
dc.subjectAdjacency list
dc.subjectScan chain
dc.subjectBoundary scan
dc.subjectDesign for testing
dc.subject.classificationVLSI and Analog Circuit Testing
dc.titleAn on-chip delay measurement using adjacency testable scan design
dc.typeArticle

Files

Collections

All