Efficient Processing Time with Carry-lookahead Adder Memristor Rationed Logic

dc.contributor.authorSuparlerk Yamtim
dc.contributor.authorSiraphop Tooprakai
dc.date.accessioned2026-05-08T19:23:24Z
dc.date.issued2023-6-1
dc.description.abstractThis paper presents a novel approach to the design of full adder circuits, leveraging the unique properties of memristors and CMOS logic in a hybrid system. This paper explores the design and operation of memristor-based logic gates, including AND, OR, NAND, and NOR gates, realized through CMOS inverters. This paper further proposes a full adder circuit using Hybrid Memristor-CMOS logic and a carry look-ahead adder (CLA). Our simulations demonstrate that the proposed full adder circuit outperforms traditional RCA-based circuits in terms of speed. This work contributes to the ongoing discourse in digital electronics, offering fresh perspectives and potential solutions to existing challenges, and hope it will inspire further research in the field of memristor-based digital electronics.
dc.identifier.doi10.1109/iceast58324.2023.10157885
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/19034
dc.subjectAdvanced Memory and Neural Computing
dc.subjectFerroelectric and Negative Capacitance Devices
dc.subjectNeuroscience and Neural Engineering
dc.titleEfficient Processing Time with Carry-lookahead Adder Memristor Rationed Logic
dc.typeArticle

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