A Logarithmic Level-Crossing ADC with Fixed Comparison Window
| dc.contributor.author | Silar Sirimasakul | |
| dc.contributor.author | A. Thanachayanont | |
| dc.date.accessioned | 2026-05-08T19:16:54Z | |
| dc.date.issued | 2022-5-24 | |
| dc.description.abstract | This paper describes the design and realization of a logarithmic level-crossing analog-to-digital converter with fixed comparison window. The proposed circuit comprises two comparators, a logarithmic charge-sharing digital-to-analog converter, a control logic circuit, and an up/down counter. The circuit is designed and simulated with process parameters from a 0.18 μm CMOS technology and a 1.8 V power supply voltage. Simulation results showed that the overall circuit exhibited the minimum resolution of 3.9mV and the maximum INL and DNL errors of -0.17LSB and -0.09LSB, respectively. | |
| dc.identifier.doi | 10.1109/ecti-con54298.2022.9795458 | |
| dc.identifier.uri | https://dspace.kmitl.ac.th/handle/123456789/15762 | |
| dc.publisher | 2022 19th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON) | |
| dc.subject | Analog and Mixed-Signal Circuit Design | |
| dc.subject | CCD and CMOS Imaging Sensors | |
| dc.subject | Low-power high-performance VLSI design | |
| dc.title | A Logarithmic Level-Crossing ADC with Fixed Comparison Window | |
| dc.type | Article |