A GHz analog multiplier for UWB communications

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dc.contributor.authorHidayat, R.
dc.contributor.authorDejhan, K.
dc.contributor.authorMoungnoul, P.
dc.contributor.authorMiyanaga, Y.
dc.date.accessioned2026-08-06T09:55:52Z
dc.date.available2026-08-06T09:55:52Z
dc.date.issued2007-12-01
dc.description.abstractA gigahertz wideband analog multiplier is proposed. The multiplier based on the MOS cascade operation circuit. The inputs are in voltage mode and become in current mode after multiplication. The result shows that the multiplier can be applied for UWB communications. The circuit is based on 0.18 μm CMOS technology simulated using HSPICE with level 49. ©2007 IEEE.
dc.identifier.citation2007 Asia Pacific Conference on Communications Apcc, 55-58, 2007
dc.identifier.doi10.1109/APCC.2007.4433502
dc.identifier.other2-s2.0-50349096690
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/1795
dc.source2007 Asia Pacific Conference on Communications Apcc
dc.titleA GHz analog multiplier for UWB communications
dc.typeConference Paper

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