Optimal Number of Wires for Circuits on RTLDesigned FPGAs

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dc.contributor.authorSato, Tomoaki
dc.contributor.authorHayashihara, Yuya
dc.contributor.authorYokota, Shione
dc.contributor.authorChivapreecha, Sorawat
dc.contributor.authorMoungnoul, Phichet
dc.date.accessioned2026-08-06T10:44:29Z
dc.date.available2026-08-06T10:44:29Z
dc.date.issued2024-01-01
dc.description.abstractFPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
dc.identifier.citationProceeding 12th International Electrical Engineering Congress Smart Factory and Intelligent Technology for Tomorrow Ieecon 2024, 2024
dc.identifier.doi10.1109/iEECON60677.2024.10537940
dc.identifier.other2-s2.0-85195788845
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/15219
dc.sourceProceeding 12th International Electrical Engineering Congress Smart Factory and Intelligent Technology for Tomorrow Ieecon 2024
dc.subjectadder circuit
dc.subjectASIC
dc.subjectFPGA
dc.subjectHDL
dc.subjectRTL
dc.subjectwiring
dc.titleOptimal Number of Wires for Circuits on RTLDesigned FPGAs
dc.typeConference Paper

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