Extraction of BSIM3v3 Junction Capacitance Model of NMOSFET in VLSI Devices,Circuits and Systems

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dc.contributor.authorA. Ruangphanit
dc.contributor.authorR. Pedlub
dc.contributor.authorR. Muanghlua
dc.date.accessioned2025-07-21T06:00:10Z
dc.date.issued2018-07-01
dc.identifier.doi10.1109/ecticon.2018.8619921
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/7576
dc.subjectParasitic capacitance
dc.subjectDiffusion capacitance
dc.subjectDifferential capacitance
dc.subject.classificationIntegrated Circuits and Semiconductor Failure Analysis
dc.titleExtraction of BSIM3v3 Junction Capacitance Model of NMOSFET in VLSI Devices,Circuits and Systems
dc.typeArticle

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