A CMOS voltage-controlled floating resistance circuit with temperature compensated

dc.contributor.authorP. Prommee
dc.contributor.authorM. Somdunyakanok
dc.contributor.authorK. Khaw-ngam
dc.contributor.authorK. Dejhan
dc.date.accessioned2025-07-21T05:48:28Z
dc.date.issued2006-01-18
dc.identifier.doi10.1109/iscit.2005.1566846
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/907
dc.subjectLinearity
dc.subjectVoltage multiplier
dc.subject.classificationAnalog and Mixed-Signal Circuit Design
dc.titleA CMOS voltage-controlled floating resistance circuit with temperature compensated
dc.typeArticle

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