Efficient parallel architecture for implementation of the CMA adaptive antenna

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dc.contributor.authorBoonpoonga, Akkarat
dc.contributor.authorSirisuk, Phaophak
dc.contributor.authorKrairiksh, Monai
dc.date.accessioned2026-08-06T10:06:52Z
dc.date.available2026-08-06T10:06:52Z
dc.date.issued2013-07-01
dc.description.abstractThis paper presents an efficient parallel architecture for implementation of a constant modulus algorithm (CMA) adaptive array antenna. By inserting delay units into the original CMA, a novel delayed CMA (DCMA) that can significantly reduce the associated critical path is derived. Consequently, a pipelining architecture that supports parallel processing is introduced for implementation of the DCMA. In addition to the pipelining technique, a power-of-two multiplier is proposed for the DCMA leading to the efficient FPGA implementation. The effects of delays and finite word-length on the convergence property of CMA are investigated via simulations. Moreover, the synthesized results demonstrate that FPGA implementation of the proposed architecture using power-of-two arithmetic achieves 26.9% resource reduction in comparison with that of fixed-point arithmetic and operating clock frequency higher than 65 MHz. The implemented FPGA was tested to confirm that the designed architecture operates well for CMA.
dc.identifier.citationIETE Technical Review Institution of Electronics and Telecommunication Engineers India, 30(4), 303-312, 2013
dc.identifier.doi10.4103/0256-4602.116719
dc.identifier.issn02564602
dc.identifier.other2-s2.0-84883625874
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/4933
dc.sourceIETE Technical Review Institution of Electronics and Telecommunication Engineers India
dc.subjectAdaptive antenna
dc.subjectConstant modulus algo-rithm
dc.subjectField programmable gate array
dc.subjectPipelining.
dc.titleEfficient parallel architecture for implementation of the CMA adaptive antenna
dc.typeArticle

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