A compact floating and grounded memristor model using single active element

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dc.contributor.authorPrasad, Sagar Surendra
dc.contributor.authorKumar, Prashant
dc.contributor.authorRaj, Niranjan
dc.contributor.authorSharma, Pankaj Kumar
dc.contributor.authorPriyadarshini, Bindu
dc.contributor.authorRanjan, Rajeev Kumar
dc.contributor.authorPrommee, Pipat
dc.date.accessioned2026-08-06T10:38:23Z
dc.date.available2026-08-06T10:38:23Z
dc.date.issued2022-12-01
dc.description.abstractMemristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.
dc.identifier.citationAEU International Journal of Electronics and Communications, 157, 2022
dc.identifier.doi10.1016/j.aeue.2022.154426
dc.identifier.issn14348411
dc.identifier.other2-s2.0-85140003594
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/13588
dc.sourceAEU International Journal of Electronics and Communications
dc.subjectActive element
dc.subjectCMOS
dc.subjectCurrent mode
dc.subjectDVCCTA
dc.subjectMemristor Emulator (MRE)
dc.subjectMonte-Carlo
dc.subjectPinched hysteresis loop (PHL)
dc.titleA compact floating and grounded memristor model using single active element
dc.typeArticle

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