Acceleration of scan-based on-chip delay measurement using extra latches and multiple asynchronous transfer scan chains

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dc.contributor.authorKentaro Kato
dc.contributor.authorSomsak Choomchuay
dc.date.accessioned2025-07-21T05:56:14Z
dc.date.issued2015-10-01
dc.identifier.doi10.1109/iciteed.2015.7409001
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/5349
dc.subjectScan chain
dc.subjectAsynchronous circuit
dc.subject.classificationVLSI and Analog Circuit Testing
dc.titleAcceleration of scan-based on-chip delay measurement using extra latches and multiple asynchronous transfer scan chains
dc.typeArticle

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