Fine-tuning of wave-pipelines on FPGAs developed by the RTL design

A wave-pipeline is a design technique for achieving high-speed and low-power operations also in field-programmable gate arrays (FPGAs). It realizes pipeline operations by adjusting delay times. Implementation of fine-tuning of wave-pipelines is possible to further increase the throughput. However, in the FPGA, it is not able to be executed by the restriction on the structure. This paper proposes a fine-tuning method for the FPGA developed by the register-transfer level (RTL) design. Although the RTL design of the FPGA has various advantages, it is required for a high-speed design for a routing delay which is larger than that of a conventional FPGA. The method is timing adjustment using a connection block with the RTL design. Results of analysis of the connection block show that the seven stages of the delay adjustment are possible in the block. In addition, the block can be used for rough-tuning of delay times. It is the area of less than half of the logic block.