Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures

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dc.contributor.authorSato, Tomoaki
dc.contributor.authorMurakami, Anyu
dc.contributor.authorChivapreecha, Sorawat
dc.contributor.authorMoungnoul, Phichet
dc.date.accessioned2026-08-06T10:48:00Z
dc.date.available2026-08-06T10:48:00Z
dc.date.issued2025-01-01
dc.description.abstractRTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4.
dc.identifier.citationProceedings of SPIE the International Society for Optical Engineering, 13518, 2025
dc.identifier.doi10.1117/12.3058686
dc.identifier.issn0277786X
dc.identifier.other2-s2.0-85219535389
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/16139
dc.sourceProceedings of SPIE the International Society for Optical Engineering
dc.subjectFPGA
dc.subjectLogic Block
dc.subjectLUT
dc.subjectNetwork Application
dc.subjectRTL
dc.titleApplication-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures
dc.typeConference Paper

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