Optimal Number of Wires for Circuits on RTLDesigned FPGAs

Abstract

FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.