Implementation of vedic multiplier technique on multicore processor

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dc.contributor.authorPanwit Tuwanuti
dc.contributor.authorNopphagaw Thongbai
dc.date.accessioned2025-07-21T05:55:15Z
dc.date.issued2014-10-01
dc.identifier.doi10.1109/tencon.2014.7022325
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/4794
dc.subjectTUTOR
dc.subjectMulti-core processor
dc.subject.classificationLow-power high-performance VLSI design
dc.titleImplementation of vedic multiplier technique on multicore processor
dc.typeArticle

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