Theoretical Analysis of Highly Linear Tunable Filters Using Switched-Resistor Techniques

Abstract

In this paper, an in-depth analysis of switched-resistor (S-R) techniques for implementing low-voltage low-distortion tunable active- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> filters is presented. The S-R techniques make use of switch(es) with duty-cycle-controlled clock(s) to achieve tunability of the effective resistance and, hence, the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> time constant. The characteristics of two S-R networks utilizing one set (S-1R) and two sets (S-2R) of switch and resistor combinations are analyzed. It will be shown that the S-2R network outperforms the S-1R counterpart in terms of finite-slew-rate-induced distortion, frequency translation, and noise performance. In order to extend the tuning range, an S-R bank scheme is also described. The theoretical analysis was verified by an experiment on a 100-kHz first-order S-R filter prototype, implemented using discrete elements, where several advantages of the S-2R over the S-1R networks are demonstrated. Simulations of 10-MHz low-pass filters based on the S-1R and S-2R techniques in a standard 0.18- mum CMOS process are also included for performance comparison in practical on-chip filter implementations.