1.2 V Differential Difference Current Conveyor Using MIGD MOST Technique

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dc.contributor.authorPunnavich Phatsornsiri
dc.contributor.authorUsa Torteanchai
dc.contributor.authorManurak Rattanasuttikan
dc.contributor.authorWirote Jongchanachavawat
dc.contributor.authorMontree Kumngern
dc.contributor.authorFabian Khateb
dc.date.accessioned2026-05-08T19:22:54Z
dc.date.issued2022-5-24
dc.description.abstractThis paper presents a new differential difference current conveyor (DDCC) using multiple-input gate-driven MOS transistor (MIGD MOST) technique. The MIGD MOST technique can be reduced the number of transistor differential pair. The differential input stage is implemented by flipped voltage follower to obtain low power supply requirements. Thus, the proposed DDCC is capable to working with a supply voltage of 1.2 V and it consumes a 44.2 µW of power dissipation. The simulations were performed with PSPICE using the 0.18 μm CMOS technology to prove the workability of the new circuit.
dc.identifier.doi10.1109/ecti-con54298.2022.9795466
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/18792
dc.publisher2022 19th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)
dc.subjectAnalog and Mixed-Signal Circuit Design
dc.subjectAdvancements in Semiconductor Devices and Circuit Design
dc.subjectLow-power high-performance VLSI design
dc.title1.2 V Differential Difference Current Conveyor Using MIGD MOST Technique
dc.typeArticle

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