The CMOS analog multiplier free from mobility reduction

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dc.contributor.authorK. Dejhan
dc.contributor.authorN. Suwanchatree
dc.contributor.authorP.P.I. Chaisayun
dc.date.accessioned2025-07-21T05:48:07Z
dc.date.issued2005-04-12
dc.identifier.doi10.1109/iscit.2004.1412442
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/725
dc.subjectVoltage multiplier
dc.subject.classificationAnalog and Mixed-Signal Circuit Design
dc.titleThe CMOS analog multiplier free from mobility reduction
dc.typeArticle

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